Flash EPROM devices, sometimes referred to as flash memory devices, typically include at least one memory array organized into rows and columns of flash memory cells. The array is typically partitioned into blocks, each of which is further divided into sectors. A row decoder and a column decoder are used to select a single row and at least one column of memory cells based upon the value of an externally generated address applied to the flash memory device. Sense amplifiers are coupled to column lines corresponding to the columns of memory cells to amplify the voltage levels on the addressed column lines corresponding to the data values stored in the addressed flash memory cells. The particular implementations of known arrays and row/column decoders will not be discussed further herein.
It is known for memory devices to have defects which can prevent the device from operating as designed. In particular, defects can occur during the manufacture of flash memory devices so that memory cells within the array do not operate properly. For example a defect in a memory cell (or associated circuitry) can cause data written to the memory cell to be stored incorrectly or not at all. Furthermore, the defect may prevent the data from being reliably read from the addressed memory cell. Any of these types of defects can reduce the manufacturing yield for the flash memory device.
It is know to include redundant memory cells in the flash memory, which can selectively replace normal memory cells that are determined to be defective to improve the manufacturing yield of the flash memory. Some flash memory devices, utilize non-volatile registers to store addresses of memory cells that are known to be defective. The addresses associated with the defective memory cells can be stored in the registers and compared to addresses associated with memory operations (i.e., read operations and write operations). If the address matches an address stored in the register, a redundant circuit can re-route (or map) the data to or from the memory so that the defective memory cells are not used for the memory operation. For example, during a write operation, write data (which would otherwise be directed to a known defective memory cell) can be re-routed to a redundant memory cell. Later, when a read operation is directed to the address of the known defective memory cell, the redundant memory cell, as well as the known defective memory cells, is accessed. The data retrieved from the redundant memory cell is re-routed to replace the data that was read from the known defective memory cell to provide the data that was previously written to the accessed address.
FIG. 1 illustrates a conventional multi-bank flash memory device 100. In particular, the conventional multi-bank flash memory device includes two banks: BANK0 101 and BANK1 102. Each of the banks has an associated row and column decoder that selects a set of memory cells in the respective bank to be accessed based on an address provided to the respective row/column decoder. BANK0 101 has an associated row decoder 111 and a column decoder 121 that receive respective addresses via address lines ABANK0. Similarly, BANK1 102 has an associated row decoder 112 and a column decoder 122 which select memory cells within the BANK1 102 to be accessed based on addresses provided via address lines ABANK 1.
Each of the respective banks also includes redundant memory cells that can be accessed with the normal memory cells associated therewith. Accordingly, when data is written normal memory cells (or read from normal memory cells), data is also written to (or read from) the redundant memory cells selected by the respective row/column decoders.
The addresses are provided to the respective banks by address buffers 171 and 172. In particular, address buffer 171 provides the addresses for the row/column decoders 111, 121 associated with BANK0 101 whereas address buffer 172 provides the addresses for the row/column decoders 112, 122 associated with BANK1 102. Accordingly, different addresses can be provided to the different banks.
Data can be provided to/from the respective banks to a respective combination of sense amplifiers and write drivers dedicated to each of the banks. In particular, data to be written to BANK0 101 is provided by a write driver 151 via data lines BANK0DL whereas data to be written to BANK1 102 is provided by a write driver 152 via data lines BANK1DL. Data read from BANK0 101 is provided to a sense amplifier 141 via data lines BANK0DL (i.e., the same lines used to provide write data to the BANK0 101). Data read from BANK1 102 is provided to a sense amplifier 142 via data lines BANK1DL (i.e., the same lines used to provide write data to BANK1 102). The data written to (or read from) either of the banks flows to/from the memory device via a data input/output buffer 160.
Each of the banks has an associated redundancy circuit. In particular, BANK0 101 has an associated redundancy circuit 131 whereas the BANK1 102 has an associated redundancy circuit 132. The redundancy circuits 131, 132 provide redundancy entries which identify memory cells within the respective bank that are known to be defective. In particular, the redundancy circuit 131 can include up to 4 entries each of which can identify an address within BANK0 101 which is known to include a defective memory cell. Similarly, the redundancy circuit 132 can include up to 4 entries each of which can identify a known defective memory cell within BANK1 102. As briefly discussed above, the entries in the redundancy circuits 131, 132 can be used to avoid known defective memory cells.
FIG. 2, illustrates a general write operation carried out in BANK0 101. In particular, an address for the write operation is provided to BANK0 101 so that the normal and redundant cells associated with the address within the bank can be accessed. The address is also provided to the redundancy circuit 131. The redundancy circuit 131 compares the address used for the write operation with the addresses of known defective memory cells in the BANK0 101. If the address for the write operation matches an address of a known defective memory cell within the bank, the redundancy circuit 131 provides information associated with the matching address that can be used to write some of the data to a redundant memory cell rather than to a known defective memory cell.
The redundancy circuit 131 provides BANK0 REPAIR INFORMATION to a multiplexer 153 included within the data input/output buffer 160 shown in FIG. 1. The multiplexer 153 “maps” the data bit within the data word DATA that would otherwise be written to the known defective memory cell to a redundant data line coupled to the redundant memory cell associated with the address in BANK0 101 to be written. Accordingly, the conventional system shown in FIG. 1 can avoid writing data to known defective memory cells by, instead, storing data in redundant cells associated with the same address.
FIG. 3 generally illustrates a read operation directed to BANK0 101 shown in FIG. 1. The address for the read operation is provided to both the normal cells and the redundant cells in BANK0 101 so that data can be retrieved from both the normal cells and the redundant cells. In particular, NORMAL DATA BITS are retrieved from the normal memory cells whereas the REDUNDANT DATA BIT is retrieved from the redundant memory cell having the same address as the normal memory cells that are accessed. The NORMAL DATA BITS and the REDUNDANT DATA BIT are provided to the sense amplifier 141.
In addition to providing the address for the read operation to the normal and redundant cells of BANK0 101, the address is also provided to the redundancy circuit 131 that includes the entries identifying the known defective memory cells in the BANK0 101. The redundancy circuit 131 compares the address provided to the BANK0 101 with the addresses associated with the known defective memory cells in BANK0 101. If the address for the read operation matches any of the addresses of known defective memory cells in BANK0 101, BANK0 REPAIR INFORMATION is provided to a multiplexer included in the sense amplifier 141. The BANK0 REPAIR INFORMATION provided by the redundancy circuit 131 identifies which bit included in the DATA retrieved from the normal cells of BANK0 101 is known to be defective. Accordingly, the multiplexer maps the bit retrieved from the redundant cell in BANK0 101 to replace the bit of the DATA retrieved from the normal memory cells which is known to be defective. The multiplexer provides the “repaired” DATA as output.
FIG. 4 illustrates a multi-bank flash memory device 200 that is similar to the structure shown in FIG. 1, but includes 16 banks rather than 2 banks. The operation and structure of the multi-bank system shown in FIG. 4 is similar to that described in reference to FIGS. 1-3. In particular, each of the banks 0 to 15 has an associated redundancy circuit each of which can include up to four entries. The entries within each of the redundancy circuits can identify a known defective memory cell within its corresponding bank. For example, redundancy circuit 231 includes up to four entries each of which can identify a known defective memory cell in the BANK0 associated with the redundancy circuit 231. Likewise, redundancy circuits 232, 233, 234 can each include up to four entries, each of which can identify a known defective memory cell in banks BANK1, BANK14, and BANK 15 respectively.
Redundant memory cells for flash memory devices are also discussed in U.S. Pat. No. 6,469,932 to Roohparvar et al., and in U.S. Pat. No. 6,381,174 to Roohparvar et al., the contents of which are incorporated herein by reference.